1. Field of the Invention
The present invention relates to a semiconductor memory device provided with a sense amplifier.
2. Description of the Prior Art
A conventional semiconductor memory device provided with a sense amplifiers will be described hereinbelow with reference to FIGS. 1 and 2.
FIG. 1 ia a schematic block diagram showing an example of the conventional semiconductor memory device of a sense amplifier. In the drawing, an address signal Add inputted to the semiconductor memory device is converted into a control signal by a decode circuit 71. On the basis of the control signal, a memory cell in a memory cell array 72 can be selected. One of a pair of transistors of the selected memory cell outputs stored information to a data line DL, and the other thereof outputs the stored information to a data line /DL (the symbol / denotes inverted logic). The outputted stored information is inputted to an equalizer circuit 73 and a sense amplifier 74 via these data lines DL and /DL.
On the other hand, the above-mentioned address signal Add is also inputted to an address transition detector circuit 88. This address transition detector circuit 88 detects whether the value of the inputted address Add transits or not, and outputs an equalize control pulse .PHI..sub.EQ to the equalizer circuit 73 when the value of the address signal Add transits (i.e., a new address has been designated).
In response to the equalize control pulse .PHI..sub.EQ from the address transition detector circuit 88, the equalizer circuit 73 sets the voltage levels of the two data lines DL and /DL to a predetermined level.
Furthermore, being delayed by a delay circuit 86, the equalize control pulse .PHI..sub.EQ is given to the sense amplifier 74 as a sense amplifier activating signal ACT. When the sense amplifier activating signal ACT is turned on or active (i.e., at a "high" level), the sense amplifier 74 compares the potential of the line DL with that of the line /DL, and outputs a "low" level signal as an output SO and a "high" level signal as an output /SO if DL&gt;/DL, respectively. In contrast with this, if DL&lt;/DL, the sense amplifier 74 outputs a "high" level signal as an output SO and a "low" level signal as an output /SO. Further, when the sense amplifier activating signal ACT is turned off or non-active, no signal is outputted.
These output data SO and /SO are outputted to two buses BUS and /BUS via a buffer 75, respectively, and further outputted to the external circuit through an output buffer 76.
FIG. 2 is a practical circuit diagram showing an example of the sense amplifier 74, which is constructed by a circuit composed of two pMOS transistors 77 and 78 and two nMOS transistors 79 and 80, a circuit composed of two pMOS transistors 81 and 82 and two nMOS transistors 83 and 84, and an nMOS transistor 85. The sense amplifier 74 activating signal ACT is inputted to the gate of the nMOS transistor 85. In the conventional sense amplifier as described above, consumed current Ia always flows as long as the sense amplifier activating signal ACT is turned on.
In the conventional semiconductor memory device constructed as described above, in usual the sense amplifier activating signal ACT is kept turned on when the device is being operated. In other words, the sense amplifier 74 is maintained always under the activated condition.
In the case where the sense amplifier 74 is maintained under the activated condition, however, since current always flows through the sense amplifier 74, the current consumption inevitably increases.
The above-mentioned drawbacks have become serious more and more, with the recent technical progress of the semiconductor memory devices to larger capacitance and higher speed.
To overcome the above-mentioned problem, there has been proposed a semiconductor memory device which can reduce the current consumption Ia by reducing the time when the sense amplifier activating signal ACT is kept turned on.
In the semiconductor memory device as described above, however, it is necessary to provide a sufficient margin with respect to the time when the sense amplifier activating signal ACT is kept turned on. This is because the reliability of the operation must be secured, under due consideration of the setting error of the delay time determined by the delay circuit 86. The setting error may be produced by the dispersion caused during the manufacturing process or the modification or fluctuations of the operating conditions. Accordingly, when a high speed access is repeated continuously in a short cycle, the time when the sense amplifier activating signal ACT is kept turned off is very short, with the result that a sufficient effect may not be expected.
In addition, a relatively long wire is required to turn on the sense amplifier activating signal ACT according to locations for taking our signals, thus raising another problem in that the signal is delayed though the long wire.
Further, it may be possible to construct the buffer circuit by use of latch circuits in order to control the sense amplifier activating signal ACT on the basis of the output signal of the latch circuits. In this case, however, it is rather difficult to set the latch timing at high speed, with the result that the control operation is not easy in the case of the semiconductor memory device of asynchronization type.